A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration

This paper presents a 1.9-ps 8× phase interpolation time-to-digital converter (PI-TDC). architecture enhances the resolution and conversion speed in cooperation with interpolation, high-frequency readout, reset techniques. The prototype PI-TDC is designed 65-nm CMOS process 1-V power supply, achieving at 2.5-GS/s. simulated DNL 0.85-LSB, INL 0.64-LSB. applied to high-speed time-based analog-to-digital (TB-ADC) high-performance voltage-to-time (VTC) capacitance compensation self-calibration (CCS-CAL). TB-ADC achieves 8-bit 1.6-GS/s PVT robustness while exhibiting Walden FoM of 52.1-fJ/conv.-step.